1. Field of the Invention
The present invention generally relates to integrated circuits and, more particularly, to a method of isolating scan paths used for testing logic designs.
2. Description of the Prior Art
Integrated circuits are used in a wide variety of products, and many of these circuits, such as microprocessors, adapter chips, etc., have complicated logic designs. These designs are often buried in the microchip layers and can be difficult to test. A generalized integrated circuit is shown in FIG. 1. Circuit 10 includes several logic function circuits 12, 14, 16, and 18 and several flip-flops, or latches, 20, 22, 24, 26, and 28. The logic functions have various inputs, and their outputs are connected to various latches; for example, logic function 12 has four outputs respectively connected to latches 20-26. Each logic function has many logic components (gates, inverters, etc.) arranged to provide a particular function, such as an adder or execution unit. The latches store data, and may provide inputs to other logic functions, such as latches 20 and 24 which are connected to logic function 16. Circuit 10 may have one or more latches such as 28, which provides the output of the circuit. A clock signal 30 provides synchronization (control) for the latches. The clock may be a primary input to the circuit or internally generated.
Those skilled in the art will appreciate that, in this example, the circuit is greatly simplified since there are many more logic functions and latches in a typical integrated circuit, the logic functions can further be very complicated, and more than one clock signal can be provided. This figure is still adequate, however, for understanding how testing of the circuit can be performed. One method involves the use of test patterns which are fed into the primary inputs of the circuit while the output is examined. This approach is limited by the structure of the logic design and may fail to catch unusual flaws in a particular design.
Another testing approach is to provide a mechanism for setting the latches to predefined states using special lines which are provided on the microchip, such as scan line 32 which is connected directly to latch 20, and scan line 34 which directly interconnects latch 20 with latch 28 (other scan lines, not shown, can be provided for other latches, depending upon the type of scan implementation). Separate control can be provided for scanning the latches, using a test clock 36. A scan output line 38 may also be provided. Conventional scan designs include the multiplexed D Flip-Flop scan design, and IBM's Level Sensitive Scan Design (LSSD). See also U.S. Pat. Nos. 4,698,588, 4,782,283, and 5,032,783.
Logic designs using such scan techniques suffer some system delay penalty due to the extra loading on the latches/flip-flops which arise from the scan path wires. In other words, it takes longer for the output of the latch to change its state because of the required charging (or discharging) of the scan lines; this delay is a function of the RC constant of the wire. The delay occurs whether the system is being tested or not, i.e., the loads are not needed for normal system function, and so, it slows down normal operation of the circuit. Conversely, if the circuit is run at a very high clock speed, logic errors may occur.
Additional problems arise from scan paths, such as excess power consumption and power-supply noise due to varying switching activity (between high and low states) during circuit operation. Scan path switching (from zero to one or one to zero) unnecessarily adds to circuit power consumption and power-supply noise. It would, therefore, be desirable to devise a method of isolating the scan paths during normal circuit operation so as to not slow down performance, and it would be particularly advantageous if the method also reduced power consumption and unnecessary switching noise. Techniques such as those shown in U.S. Pat. No. 4,495,629 achieve some of these objectives, but require modifying system scannable storage elements, which can introduce additional limitations.